Write verilog code for OR gate using different modeling behaviour.

Create a or gate using half adders and simply the equation to a + b

Follow to the fourth. Build a design where a logic high is given when odd number of ones enters in a bit stream?

Write truth table for even and odd parity for 3 input variables and draw the logic gate structure for the same?

How to make a 27* 1 decoder using 3* 1 decder

Draw Xor gate with using Nor gate only